The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same. More particularly, the invention relates to a semiconductor integrated circuit device comprising an SRAM (static random access memory). A general description of the SRAM is found illustratively in IEDM (International Electron Device Meeting), Tech. Dig., pp. 477-480, 1991.
As a semiconductor memory, the SRAM comprises memory cells each composed of a flip-flop circuit and two transfer MISFETs (metal insulator semiconductor field effect transistors) at an intersection formed by complementary data lines and word lines.
Each transfer MISFET constituting part of a memory cell has one of its semiconductor regions connected to the I/O terminals of the flip-flop circuit; the other semiconductor region is connected to one complementary data line. The word lines, connected to the gate electrodes of the transfer MISFETs, control the conduction thereof.
The flip-flop circuit of each memory cell is constituted as a data retaining unit made of two driver MISFETs and two load resistance elements. Each driver MISFET has one of its semiconductor regions (drain) connected to one semiconductor region of one transfer MISFET; the other semiconductor region (source) of the driver MISFET is connected to a reference voltage line. The gate electrode of the driver MISFET is connected to the other semiconductor region of the transfer MISFET.
One end of each load resistance element is connected to one semiconductor region of each transfer MISFET. The other end of the load resistance elements is connected to supply voltage lines. The load resistance elements are deposited in layered fashion on top of the driver MISFETs in order to reduce the memory cell area for higher integration.
Recent years have seen SRAMs of the above-described type further integrated to accommodate large amounts of data and to operate at high speeds. This type of SRAM is described illustratively in U.S. Pat. No. 5,239,196 (U.S. Ser. No. 653,493), assigned to the assignee of the present application on Feb. 11, 1991 with the United States Patent and Trademark Office.
The technology disclosed in the above document primarily involves forming in each memory cell the gate electrodes of the driver MISFETs and those of the transfer MISFETs (word lines) using different conductive strips. The drive and transfer MISFETs intersect with one another in their gate length direction. The word lines extend in the gate length direction of the gate electrodes of the driver MISFETs, and intersect with part of these gate electrodes.
According to the prior art above, part of the driver MISFETs is made to overlap with part of the word lines. The structure reduces the memory cell area, in the gate width direction of the driver MISFETs, by the amount equivalent to the overlapping region. Thus the degree of integration of the SRAM is enhanced.
The above technology also involves connecting in each memory cell a first word line to the gate electrode of a first transfer MISFET while connecting a second word line to the gate electrode of a second transfer MISFET, the second word line being separated from the first word line and extending in the same direction of the latter. Between the first and the second word lines are a first and a second driver MISFET. The first driver MISFET has its drain region connected to one semiconductor region of the first transfer MISFET. The second driver MISFET has its drain region connected to one semiconductor region of the second transfer MISFET. The plane shape of the first transfer and driver MISFETs and that of the second transfer and driver MISFETs are arranged to be symmetrical around the center point of each memory cell. The gate width size of the first and the second transfer MISFETs is made smaller than that of the first and the second driver MISFETs.
The above-described construction inside the memory cell allows for greater margins of alignment in photolithography between the first and the second transfer MISFETs as well as between the first and the second driver MISFETs. The construction contributes to reducing size disparities among the memory elements while ensuring stable memory cell operation. With each memory element reduced in size, the memory cell area is reduced and the SRAM is boosted in terms of integration.
The above technology makes it possible to determine uniquely the separation inside each memory cell between the first transfer MISFET and first driver MISFET on the one hand, and the second transfer MISFET and second driver MISFET on the other. The separation is so determined on the basis of the size of an element-separating region between the first and the second driver MISFETs. Because the unnecessary size (i.e., an empty region equivalent to the clearance between the driver and the transfer MISFETs) is eliminated from the size of the separation, the memory cell size is reduced and the degree of integration of the SRAM is enhanced.
Furthermore, the above technology involves connecting two word lines to the gate electrodes of the two transfer MISFETs in each memory cell. This constitution eliminates the need to wind around the word line (i.e., one word line per memory cell) inside the memory cell to connect the gate electrodes of the two transfer MISFETs. With the two word lines extending over a short distance in a substantially linear manner, the resistance values of the word lines are lowered. This translates into higher speeds at which to write and read data to and from each memory cell, which results in higher operation speeds of the SRAM.
The above technology adopts the so-called complete CMOS (complementary metal oxide semiconductor) structure. The structure involves forming the flip-flop circuit of each memory cell from two driver MISFETs and two load MISFETs in order to lower the standby current. The load MISFETs are deposited in layered fashion on the driver MISFETs to reduce the memory cell area while improving the degree of integration.
In developing new SRAMs of higher integration operating at higher speeds, the inventors of this invention noted the following problems:
The above technology has capacitor elements formed in each memory cell between the gate electrodes of the driver MISFETs and the load MISFETs deposited on top of the former. The constitution makes it difficult to provide capacitor elements of large capacitance. With the SRAM getting smaller in size, the resistance to xcex1-ray soft errors of the memory cell tends to be insufficient.
According to the above technology, each memory cell has the drain region of one driver MISFET, the gate electrode of one load MISFET, the gate electrode of the other driver MISFET, and the drain region of the other load MISFET interconnected through a plurality of contact holes. This structure tends to increase the contact hole area, which poses an impediment to reducing the memory cell area.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device and a method for manufacturing the same, the device comprising an SRAM providing each memory cell with higher resistance to xcex1-ray soft errors.
It is another object of the present invention to provide a semiconductor integrated circuit device and a method for manufacturing the same, the device affording higher degrees of SRAM integration.
It is a further object of the present invention to provide a semiconductor integrated circuit device and a method for manufacturing the same, the device providing higher SRAM operation speeds.
Other objects, features and advantages of the present invention will become apparent in the following specification and accompanying drawings.
Major features of the invention disclosed in this specification are outlined below:
(1) According to one aspect of the invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor substrate having a main surface; a plurality of memory cells constituting a static random access memory, each of the plurality of memory cells being composed of transfer MISFETs controlled by word lines and of a flip-flop circuit including driver MISFETs and load MISFETs; a first conductive strip formed over the main surface of the semiconductor substrate and constituting gate electrodes of the driver MISFETs; a second conductive strip formed over the main surface of the semiconductor substrate and constituting gate electrodes of the transfer MISFETs; a third conductive strip formed over the first and the second conductive strips and including channel regions, source regions and drain regions of the load MISFETs; a fourth conductive strip formed over the third conductive strip and constituting gate electrodes of the load MISFETs; a fifth conductive strip formed over the fourth conductive strip and constituting supply voltage lines connected to the source regions of the load MISFETs; and a dielectric film formed between the gate electrodes of the load MISFETs and the supply voltage lines; wherein the supply voltage lines and the load MISFETs are positioned relative to one another so that capacitor elements are formed between the gate electrodes of the load MISFETs and the supply voltage lines.
(2) In a preferred structure of the invention as defined in (1) above, a sixth conductive strip is formed over the first and the second conductive strips so as to constitute reference voltage lines connected to the source regions of the driver MISFETs, wherein the third conductive strip is formed over the sixth conductive strip to constitute the channel regions, source regions and drain regions of the load MISFETs, and wherein that plane part of the sixth conductive strip over which the load MISFETs are not furnished has holes formed thereon.
(3) In another preferred structure of the invention as defined in (1) above, a contact hole is formed over the drain region of one driver MISFET so as to interconnect the drain region of that one driver MISFET, the gate electrode of one load MISFET, the gate electrode of the other driver MISFET, and the drain region of the other load MISFET.
(4) In a further preferred structure of the invention as defined in (3) above, a sixth conductive strip is formed over the first and the second conductive strips so as to constitute reference voltage lines connected to the source regions of the driver MISFETs, wherein the third conductive strip is formed over the sixth conductive strip to constitute the channel regions, source regions and drain regions of the load MISFETs, and wherein the contact hole is surrounded by the second and the sixth conductive strips over which a thick insulating film is deposited.
(5) In an even further preferred structure of the invention as defined in (1) above, a sixth conductive strip is formed over the first and the second conductive strips so as to constitute reference voltage lines connected to the source regions of the driver MISFETs, wherein the third conductive strip is formed over the sixth conductive strip to constitute the channel regions, source regions and drain regions of the load MISFETs, the sixth conductive strip being formed into a pad layer over the drain regions of the transfer MISFETs so that data lines are connected via the pad layer to the drain regions of the transfer MISFETs.
(6) In a still further preferred structure of the invention as defined in (1) above, a sixth conductive strip is formed over the first and the second conductive strips so as to constitute reference voltage lines connected to the source regions of the driver MISFETs, wherein the third conductive strip is formed over the sixth conductive strip to constitute the channel regions, source regions and drain regions of the load MISFETs, the sixth conductive strip being formed into a pad layer over one semiconductor region of n-channel MISFETs constituting part of the peripheral circuits of the static random access memory, so that that one semiconductor region of the n-channel MISFETs is wired via the pad layer.
(7) In a yet further preferred structure of the invention as defined in (1) above, a sixth conductive strip is formed over the first and the second conductive strips so as to constitute reference voltage lines connected to the source regions of the driver MISFETs, wherein the third conductive strip is formed over the sixth conductive strip to constitute the channel regions, source regions and drain regions of the load MISFETs, the fifth conductive strip being formed into a pad layer over one semiconductor region of p-channel MISFETs constituting part of the peripheral circuits of the static random access memory, so that that one semiconductor region of the p-channel MISFETs is wired via the pad layer.
(8) In another preferred structure of the invention as defined in (1) above, peripheral circuits of the static random access memory include asymmetrically constructed n-channel MISFETs having source regions of a double diffused drain structure composed of a high-density n+-type semiconductor region and a low-density n-type semiconductor region, the asymmetrically constructed n-channel MISFETs further having drain regions of an LDD structure made of a high-density n+-type semiconductor region and a low-density n-type semiconductor region.
(9) In a further preferred structure of the invention as defined in (1) above, peripheral circuits of the static random access memory include n-channel MISFETs having source regions and drain regions of LDD structures each composed of a high-density n+-type semiconductor region and a low-density n-type semiconductor region, the latter region being formed over a low-density p-type semiconductor region.
(10) In an even further preferred structure of the invention as defined in (1) above, peripheral circuits of the static random access memory include p-channel MISFETs having source regions and drain regions of LDD structures each composed of a high-density p+-type semiconductor region and a low-density p-type semiconductor region, the latter region being formed over a low-density n-type semiconductor region.
(11) In a still further preferred structure of the invention as defined in (1) above, the dielectric film between those gate electrodes of the load MISFETs which are made of the fourth conductive strip on the one hand, and the supply voltage lines made of the fifth conductive strip on the other, is constituted by a silicon oxide film and a silicon nitride film, the latter film being deposited over the former in layered fashion.
(12) According to another aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device having a static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit formed by driver MISFETs and load MISFETs, the method comprising the steps of; forming gate electrodes of the driver MISFETs by use of a first conductive strip deposited over a main surface of a semiconductor substrate; forming gate electrodes of the transfer MISFETs by use of a second conductive strip deposited over the main surface of the semiconductor substrate; forming reference voltage lines connected to source regions of the driver MISFETs by use of a third conductive strip deposited over the first and the second conductive strips; forming channel regions, source regions and drain regions of the load MISFETs by use of a fourth conductive strip formed over the third conductive strip; forming a contact hole on the drain regions of the driver MISFETs; and forming gate electrodes of the load MISFETs by use of a fifth conductive strip deposited over the fourth conductive strip, so that the contact hole interconnects the drain region of one driver MISFET, the gate electrode of one load MISFET, the gate electrode of the other driver MISFET, and the drain region of the other load MISFET.
(13) According to a further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device having a static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit formed by driver MISFETs and load MISFETs, the method comprising the steps of: forming gate electrodes of the driver MISFETs by use of a first conductive strip deposited over a main surface of a semiconductor substrate; forming gate electrodes of the transfer MISFETs by use of a second conductive strip deposited over the main surface of the semiconductor substrate; forming reference voltage lines connected to source regions of the driver MISFETs by use of a third conductive strip deposited over the first and the second conductive strips; forming gate electrodes of the load MISFETs by use of a fourth conductive strip formed over the third conductive strip; forming side wall spacers on the side wall of the gate electrodes of the load MISFETs by etching an insulating film deposited over the fourth conductive strip; forming a gate insulating film of the load MISFETs over the fourth conductive strip through thermal oxidation of the latter; and forming channel regions, source regions and drain regions of the load MISFETs by use of a fifth conductive strip deposited over the gate insulating film of the load MISFETs.
(14) According to an even further aspect of the invention, there is provided a method for manufacturing a semiconductor integrated circuit device having a static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit formed by driver MISFETs and load MISFETs, the method comprising the steps of: forming gate electrodes of the driver MISFETs by use of a first conductive strip deposited over a main surface of a semiconductor substrate; forming a first insulating film over the first conductive strip; forming a second conductive strip over the first insulating film; forming source regions and drain regions of the driver MISFETs by adding impurities to the main surface of the semiconductor substrate; leaving the second conductive strip intact solely over the gate electrodes of the driver MISFETs by etching the second conductive strip; forming a second insulating film over the second conductive strip; forming a contact hole on the source regions of the driver MISFETs by etching the second insulating film and the first insulating film, in that order; etching a third conductive strip deposited over the second insulating film so as to form reference voltage lines connected to the source regions of the driver MISFETs via the contact hole, the reference voltage lines being further connected to the second conductive strip over the gate electrodes of the driver MISFETs via the side wall of the contact hole.
According to the structure described in (1) above, capacitor elements C of large capacitance are formed between the gate electrodes of the load MISFETs on the one hand, and the supply voltage lines occupying a large area over these gate electrodes on the other. This structure enhances the resistance of the memory cells to xcex1-ray soft errors.
According to the structure described in (2) above, holes are made on part of the supply voltage lines so as to reduce the resistivity thereof. The structure thus prevents drops in the supply voltage fed through the supply voltage lines to the memory cells, permitting stable SRAM operation.
According to the structure described in (3) and (13) above, one contact hole interconnects the drain region of one driver MISFET, the gate electrode of one load MISFET, the drain region of the other load MISFET, and the gate electrode of the other driver MISFET over the main surface of the semiconductor substrate. Compared with prior art setups where these conductive strips are connected via a plurality of contact holes, this single contact hole structure reduces the memory cell area by the amount equivalent to the multiple contact holes eliminated. In addition, the single contact hole structure requires fewer steps to follow for the manufacture thereof than the multiple contact hole setups.
According to the structure described in (4) above, the contact hole formed on the drain regions of the driver MISFETs is surrounded by the second and the sixth conductive strips which in turn are covered with a thick insulating film. The structure provides greater margins of alignment for the contact hole to be formed.
According to the structure described in (5) above, the data lines are connected to the drain regions of the transfer MISFETs via the pad layer made of the sixth conductive strip constituting the reference voltage lines. The structure eliminates the need for margins of alignment for the contact hole to be formed on the drain regions, whereby the area of the drain regions of the transfer MISFETs is reduced.
According to the structure described in (6) above, one semiconductor region of the n-channel MISFETs constituting part of the peripheral circuits of the SRAM is wired via the pad layer formed by the sixth conductive strip. The structure eliminates the need for margins of alignment for the contact hole to be formed on the semiconductor region, whereby the semiconductor region area of the n-channel MISFETs is reduced.
According to the structure described in (7) above, one semiconductor region of the p-channel MISFETs constituting part of the peripheral circuits of the SRAM is wired via the pad layer formed by the fifth conductive strip. The structure eliminates the need for margins of alignment for the contact hole to be formed on the semiconductor region, whereby the semiconductor region area of the p-channel MISFETs is reduced.
According to the structure described in (8) above, the asymmetrically constructed n-channel MISFETs constituting part of the peripheral circuits of the SRAM have the source regions of the so-called double diffused drain structure. This setup reduces the resistance value of the source regions and thereby improves the ability of the SRAM to be driven on currents. Furthermore, building the drain regions in the LDD structure enhances the dielectric strength of these regions.
According to the structure described in (9) above, the low-density p-type semiconductor regions are formed under the low-density n-type semiconductor regions. This structure minimizes the short channel effect of the n-channel MISFETs.
According to the structure described in (10) above, the low-density n-type semiconductor regions are formed under the low-density p-type semiconductor regions. This structure minimizes the short channel effect of the p-channel MISFETs.
According to the structure described in (11) above, the insulating film under the fifth conductive strip is constituted by a silicon oxide film and a silicon nitride film, the latter film being deposited over the former in layered fashion. When the fifth conductive strip is etched to form the supply voltage lines, the insulating film under the fifth conductive strip is protected from erosion. Thus the structure improves the dielectric strength of the capacitor elements composed of the fifth conductive strip, the insulating film and the fourth conductive strip.
According to the manufacturing method described in (13) above, side wall spacers are formed on the side wall of the gate electrodes of the load MISFETs. The side wall spacers protect the edges of the gate electrodes. Thermally oxidizing the gate electrodes rounds the edges thereof, which improves the dielectric strength of the gate insulating film of the load MISFETs. Furthermore, the gate insulating film has a higher dielectric strength when formed by thermal oxidation than by the CVD method.
According to the manufacturing method described in (14) above, capacitor elements are formed between the gate electrodes of the driver MISFETs and the reference voltage lines. The second conductive strip is formed between the first and the second insulating films constituting the dielectric film of the capacitor elements. This arrangement makes it possible effectively to reduce the thickness of the dielectric film, whereby the capacitance of the capacitor elements is boosted.
A brief description below of the drawings accompanying this specification will be followed by a detailed description of preferred embodiments of the invention. Throughout the description of the embodiments with reference to the drawings, the parts that are functionally identical are designated by like reference numerals, and any repetitive description of the same parts is omitted.